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[ak4104] ms0642-e-01 2010/09 - 1 - general description the ak4104 is a digital audio interface transmitter (dit) which supports data rate up to 192khz sample rate operation. the ak4104 encodes and transmits audio data ac cording to the aes3, iec60958, s/pdif & eiaj cp1201 interface standards. the ak4104 accepts audio and digital data, which is then encoded. the audio serial port supports four formats. features ? sampling rate up to 192khz ? support aes3, iec60958, s/pdif & eiaj cp1201 consumer formats ? generates parity bits ? 1-channel transmission output ? 42-bit channel status buffer ? supports multiple clock frequenci es: 128/192/256/384/512 /768/1024/1536fs ? supports left/right justified and i 2 s audio formats ? easy to use 4 wire/3 wire serial host interface ? cmos input level ? power supply: 2.7 to 3.6v ? small package: 16pin tssop ? temperature range of -20 to 85 c 192khz 24-bit 3.3v dit ak4104
[ak4104] ms0642-e-01 2010/09 - 2 - lrck bick audio data interface mclk pdn prescaler biphase encoder sdti1 tx cdto csn cclk cdti p interface vdd vss figure 1. ak4104 block diagram (mode= ?0?) lrck bick audio data interface mclk pdn prescaler biphase encoder sdti1 tx csn cclk cdti p interface vdd vss sdti2 figure 2. ak4104 block diagram (mode= ?1?)
[ak4104] ms0642-e-01 2010/09 - 3 - ordering guide ak4104et ? 20 +85 c 16pin tssop (0.65mm pitch) akd4104 evaluation board for ak4104 pin layout 1 mclk lrc k bic k csn ccl k cdti ak4104 top view 2 3 4 5 6 7 8 tx vdd cdto/ sdti2 vss test4 test3 test2 16 15 14 13 12 11 10 9 pdn sdti1 test1
[ak4104] ms0642-e-01 2010/09 - 4 - pin/function no. pin name i/o function 1 mclk i master clock input pin 2 bick i audio serial data clock pin 3 sdti1 i audio serial data input 1 pin 4 lrck i input channel clock pin 5 pdn i power down and reset pin ?l?: power down and reset, ?h?: power up 6 csn i chip select pin 7 cclk i control data clock pin 8 cdti i control data input pin 9 test1 i test pin this pin should be connected to vdd. 10 test2 o test pin this pin should be open. 11 test3 o test pin this pin should be open. 12 test4 o test pin this pin should be open. 13 vss - ground pin 14 vdd - power supply pin, 2.7 3.6v cdto o control data output pin, the output is ?hi-z? when pdn pin = ?l?. 15 sdti2 i audio serial data input 2 pin 16 tx o transmit channel output pin, the output is ?l? when pdn pin = ?l? or rstn bit =?0? or pw bit = ?0? or mclk stops. note: all digital input pins should not be left floating.
[ak4104] ms0642-e-01 2010/09 - 5 - absolute maximum ratings (vss=0v; note 1 ) parameter symbol min max units power supply vdd ? 0.3 4.6 v input current, any pin except supplies iin - 10 ma digital input voltage ( note 2 ) vind ? 0.3 vdd+0.3 v ambient temperature (powered applied) ta ? 20 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. mclk, bick, sdti1, lrck , pdn, csn, cclk, cdti, sdti2 warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss=0v; note 1 ) parameter symbol min typ max units power supply vdd 2.7 3.3 3.6 v note 1. all voltages with respect to ground. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet. dc characteristics (ta=25 c; vdd=2.7 3.6v) parameter symbol min typ max units power supply current ( note 3 ) normal operation (pdn pi n = ?h?, fs=44.1khz) ( note 3 ) full power-down mode (pdn pin = ?l?) ( note 4 ) 0.9 10 1.8 50 ma a high-level input voltage low-level input voltage vih vil 70%vdd - - - - 30%vdd v v high-level output voltage (iout=-80 a) low-level output voltage (iout=80a) voh1 vol1 vdd-0.4 - - - - 0.4 v v input leakage current iin - - 10 a note 3. tx pin: open . power supply current (idd@3.3v) is 1.0ma(typ)@fs=48khz, 1.4ma(typ)@fs=96khz and 2.6ma(typ)@fs=192khz. idd is 10a(typ) if pdn= ?l? and all other input pins are held to vss(@3.3v). (tx pin: 20pf, power supply current (idd@3.3v) is 3.3ma(typ)@fs=192khz.) note 4. all digital input pins are fixed to vdd or vss. tx characteristics (ta=25 c; vdd=2.7 3.6v) parameter symbol min typ max units high-level output voltage ( iout=-400 a) low-level output voltage ( iout=400 a) voh2 vol2 vdd-0.4 - - - - 0.4 v v load capacitance cl - - 50 pf
[ak4104] ms0642-e-01 2010/09 - 6 - switching characteristics (ta=25 c; vdd=2.7 3.6v, c l =20pf) parameter symbol min typ max units master clock frequency frequency duty cycle fclk dclk 2.048 40 36.864 60 mhz % lrck frequency frequency duty cycle fs dclk 8 45 192 55 khz % audio interface timing bick period bick pulse width low pulse width high bick ? ? to lrck edge ( note 5 ) lrck edge to bick ? ? ( note 5 ) sdti hold time sdti setup time tbck tbckl tbckh tblr tlrb tsdh tsds 81 30 30 20 20 20 20 ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 40 40 150 150 50 45 70 ns ns ns ns ns ns ns ns ns ns power-down & reset timing pdn pulse width ( note 6 ) tpd 150 ns note 5. bick rising edge must not occur at the same time as lrck edge. note 6. the ak4104 can be reset by bringing pdn pin = ?l?.
[ak4104] ms0642-e-01 2010/09 - 7 - timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 3. clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr figure 4. serial interface timing
[ak4104] ms0642-e-01 2010/09 - 8 - tcckl csn cclk tcds cdti tcdh tcss c0 a4 tcckh cdto hi-z r/w c1 vih vil vih vil vih vil tcck figure 5. write/read command input timing in 3-wire/4-wire serial mode tcsw csn cclk cdti d2 d0 tcsh cdto hi-z d1 d3 vih vil vih vil vih vil figure 6. write data input timing in 3-wire/4-wire serial mode csn cclk tdcd cdto d7 d6 cdti a1 a0 d5 hi-z 50%vdd vih vil vih vil vih vil figure 7. read data output timing 1 in 4-wire serial mode
[ak4104] ms0642-e-01 2010/09 - 9 - csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%vdd vih vil vih vil vih vil hi-z figure 8. read data output timing 2 in 4-wire serial mode tpd vil pdn figure 9. power-down & reset timing
[ak4104] ms0642-e-01 2010/09 - 10 - operation overview reset and initialization the ak4104 should be reset once by bringing pdn = ?l? upon power-up. it takes 8 bit clock cycles for the ak4104 to initialize after pdn pin goes ?h?. mclk and lrck relationship for correct synchronization, mclk and lrck should be derived from the same clock signal either directly (as through a frequency divider) or indirectly (for example, as through a dsp). the phase relationship between mclk and lrck should be kept after power-up. the mclk frequencies shown in table 1 are supported. the internal clock frequency is set depending on the external mclk frequency automatically. mclk fs 128fs 16k-192khz 192fs 16k-192khz 256fs 8k-128khz 384fs 8k-96khz 512fs 8k-48khz 768fs 8k-48khz 1024fs 8k-32khz 1536fs 8k-24khz table 1. mclk frequency
[ak4104] ms0642-e-01 2010/09 - 11 - audio interface format data is shifted in via the sdti pin using bick and lrck inputs. the dif1-0 bits as shown in table 2 can select four serial data modes. in all modes the serial data is msb-first, 2?s compliment format and is latched on the rising edge of bick. mode 3 can be used for 16bit i 2 s compatible format by zeroing the unused lsbs at bick 48fs or bick = 32fs. mode dif1 dif0 sdti format bick figure 0 0 0 16bit, lsb justified 32fs figure 10 1 0 1 24bit, lsb justified 48fs figure 11 2 1 0 24bit, msb justified 48fs figure 12 3 1 1 16/24bit, i 2 s compatible 48fs or 32fs figure 13 table 2. audio interface format lrck bick(32fs) 0 110 2 3 9 1112131415 0 12 3 1 0 10 9 1112131415 sdti(i) don't care 1 0 15 14 13 210 15 14 13 12 12 don't care sdti-15:msb, 0:lsb sdti(i) 15 14 13 76543 210 15 14 13 15 76543 210 bick(64fs) 0 118 2 3 19 20 31 0 1 2 3 1 0 18 19 20 31 17 17 lch data rch data figure 10. mode 0 timing lrck bick(64fs) 0 1 224310 12 1 0 31 24 89 89 sdti(i) don't care 0 8 10 23:msb, 0:lsb lch data rch data 23 8 don't care 23 1 figure 11. mode 1 timing lrck bick(64fs) 0 1 2202124310 12 1 0 22 20 21 31 24 22 23 23 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 23 1 2 3 4 figure 12. mode 2 timing
[ak4104] ms0642-e-01 2010/09 - 12 - lrck bick(64fs) 0 1 225 21 24 0 12 1 0 22 25 21 24 22 23 23 3 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 1 2 3 4 figure 13. mode 3 timing dit input select the ak4104 can select 4-wire p i/f mode (mode bit = ?0?) or 3-wire p i/f mode (mode bit = ?1?). in 3-wire p i/f mode, the ak4104 can select the input data of dit from sdti1 or sdti2 data. mode sel1 sel0 p i/f dit input 0 x x 4-wire sdti1 1 0 0 3-wire sdti1 1 0 1 3-wire sdti2 1 1 0 3-wire sdti2:dit bypass 1 1 1 reserved (x: don?t care) table 3. dit input
[ak4104] ms0642-e-01 2010/09 - 13 - data transmission format the data transmitted on the tx outputs is formatted in blocks as shown in figure 14 . each block consists of 192 frames. a frame of data contains two sub-frames. a sub-frame consists of 32 bits of info rmation. each received data bit is coded using a bi-phase mark encoding as a two binary state symbol. the preambles violate bi-phase encoding so they may be differentiated from data. in bi-phase encoding, the first state of input symbol is always the inverse of the last state of the previous data symbol. for a logic 0, the second state of the symbol is the same as the first state. for a logic 1, the second state is opposite of the first. figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states. frame 191 frame 0 frame 1 sub-frame sub-frame m channel 1 w channel 2 b channel 1 w channel 2 m channel 1 w channel 2 figure 14. block format 0 1 1 0 0 0 1 0 figure 15. a biphase-encoded bit stream the sub-frame is defined in figure 16 below. bits 0-3 of the sub-frame represent a preamble for synchronization. there are three preambles. the block preamble, b, is contained in the first sub-frame of frame 0. the channel 1 preamble, m, is contained in the first sub-frame of all other frames. the channel 2 preamble, w, is contained in all of the second sub-frames. table 4 below defines the symbol encoding for each of the preambles. bits 4-27 of the sub-frame contain the 24 bit audio sample in 2?s complement format with bit 27 as the most signifi cant bit. for 16 bit mode, bits 4-11 are all 0. bit 28 is the validity flag. it is ?h? if the audio sample is unreliable. bit 29 is a user data bit. frame 0 contains the first bit of a 192 bit user data word. frame 191 contains the last bit of the user data word. bit 30 is a channel status bit. again frame 0 contains the first bit of the 192 bit word with the last bit in frame 191. bit 31 is an even parity bit for bits 4-31 of the sub-frame. sync p c u v l m s audio sample s b b 0 3 4 27 28 29 30 31 figure 16. sub-frame format the block of data contains consecutive fr ames transmitted at a state-bit rate of 64 times the sample frequency, fs. for stereophonic audio, the left or a channel data is in channel 1 while the right or b data is in channel 2. for monophonic audio, channel 1 contains the audio data. preamble preceding state = 0 preceding state = 1 b 11101000 00010111 m 11100010 00011101 w 11100100 00011011 table 4. sub-frame preamble encoding channel status bit in the consumer mode (bit0 = ?0?), bits20-23(audio channel) must be controlled by the ct20 bit. when the ct20 bit is ?1?, the ak4104 corresponds to ?stereo mode?, bits20-23 are se t to ?1000?(left channel) in sub-frame 1, and is set to ?0100?(right channel) in sub-frame 2. when the ct20 bit is ?0?, bits20-23 is set to ?0000? in both sub-frame 1 and sub-frame 2.
[ak4104] ms0642-e-01 2010/09 - 14 - p control interface the ak4104 can select 4-wire p i/f mode (mode bit = ?0?) or 3-wire p i/f mode (mode bit = ?1?). 1.4-wire serial mode (mode bit = ?0?, default) the internal registers may be either written or read by the 4-wire p interface pins: csn, ccl k, cdti and cdto. the data on this interface consists of chip ad dress (2bits, c1/0; fixed to ?11?), read/wr ite (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data are clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operatio ns, data is latched after the 16th rising edge of cclk, after a high-to-low transition of csn. csn should be set to ?h? once after the 16th cclk. for read operations, the cdto output goes high impedance after a low-to-high transition of csn. the ma ximum speed of cclk is 5mhz. pdn pin = ?l? resets the registers to their default values. cdti cclk csn c1 0 1 2 34567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/ w c0 a 0 d0 d1 d2 d3 cdto hi-z write cdti c1 d4 d5 d6 d7 a1 a2 a3 a4 r/ w c0 a 0 d0 d1 d2 d3 cdto hi-z read d4 d5 d6 d7 d0 d1 d2 d3 hi-z c1-c0: chip address: (fixed to ?11?) r/w: read/write (0:read, 1:write) a4-a0: register address d7-d0: control data figure 17. 4-wire p i/f timing *when the ak4104 is in the power down mode (pdn pin = ?l?) or the mclk is not provided, writing into the control register is inhibited.
[ak4104] ms0642-e-01 2010/09 - 15 - 2.3-wire p i/f mode (mode bit = ?1?) internal registers may be written by 3-wire p interface pins , csn, cclk and cdti. the data on this interface consists of chip address (2bits, c1/0; fixed to ? 11?), read/write (1bit; fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). the ak4104 latche s the data on the rising edge of cclk, so data should clocked in on the falling edge. the writing of data becomes valid by 16th cclk after a high to low transition of csn. csn should be set to ?h? once after the 16th cclk. the clock speed of cclk is 5mhz (max). pdn pin = ?l? resets the registers to their default values. the in ternal timing circuit is reset by rstn bit, but the registers are not initialized. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (fixed to ?11?) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 18. 3-wire p i/f timing *the ak4104 does not support the read command and chip address. c1/0 and r/w are fixed to ?011? *when the ak4104 is in the power down mode (pdn pin = ?l?) or the mclk is not provided, writing into the control register is inhibited.
[ak4104] ms0642-e-01 2010/09 - 16 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 1 0 0 0 dif1 dif0 pw rstn 01h reserved 0 1 0 1 1 0 1 1 02h control 2 0 0 0 0 0 mode sel1 sel0 03h tx 1 0 0 0 0 0 v txe 04h channel status byte0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 05h channel status byte1 cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 06h channel status byte2 cs23 cs22 cs21 cs20 cs19 cs18 cs17 cs16 07h channel status byte3 cs31 cs30 cs29 cs28 cs27 cs26 cs25 cs24 08h channel status byte4 cs39 cs38 cs37 cs36 cs35 cs34 cs33 cs32 09h channel status byte5 0 0 0 0 0 0 cs41 cs40 notes: for addresses from 0ah to 1fh, data must not be written. when pdn pin goes ?l?, the registers are initialized to their default values. when rstn bit goes ?0?, the only internal timing is re set and the registers are not initialized to their default values. all data can be written to the regist er even if pw or rstn bit is ?0?. the ?0? register should be written ?0?, the ?1? register should be written ?1? data. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 1 0 0 0 dif1 dif0 pw rstn r/w r/w default 1 0 0 0 1 1 1 1 rstn: internal timing reset control 0: reset. all registers are not initialized. 1: normal operation pw: power down control 0: power down. all registers are not initialized. 1: normal operation dif1-0: audio data interface formats ( table 2) initial: ?11?, mode 3
[ak4104] ms0642-e-01 2010/09 - 17 - register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 0 0 0 0 0 mode sel1 sel0 r/w r/w default 0 0 0 0 0 0 0 0 mode: mode control 0: 4 wire mode 1: 3 wire mode sel1-0: dit input 00: sdti1 input 01: sdti2 input 10: sdti2 input (dit bypass) 11: reserved (note) sel1-0 bits can not us e in 4 wire mode (mode=?0?). register name d7 d6 d5 d4 d3 d2 d1 d0 03h tx 1 0 0 0 0 0 v txe r/w r/w default 1 0 0 0 0 0 0 1 v: validity flag 0: valid 1: invalid txe: tx output 0: ?l? 1: normal operation register name d7 d6 d5 d4 d3 d2 d1 d0 04h channel status byte0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 default 0 0 0 0 0 1 0 0 05h channel status byte1 cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 default 0 0 0 0 0 0 0 0 06h channel status byte2 cs23 cs22 cs21 cs20 cs19 cs18 cs17 cs16 default 0 0 0 0 0 0 0 0 07h channel status byte3 cs31 cs30 cs29 cs28 cs27 cs26 cs25 cs24 default 0 0 0 0 0 0 0 0 08h channel status byte4 cs39 cs38 cs37 cs36 cs35 cs34 cs33 cs32 default 0 0 0 0 0 0 0 0 09h channel status byte5 0 0 0 0 0 0 cs41 cs40 default 0 0 0 0 0 0 0 0 cs7-0: transmitter channel status byte 0 default: ?00000100? cs39-8: transmitter channel status byte 4-1 default: ?00000000? cs41-cs40: transmitter channel status byte 5 default: ?00000000?, d7-d2 bits should be written ?1?.
[ak4104] ms0642-e-01 2010/09 - 18 - system design figure 19 and figure 20 show the system connection diagram. th e evaluation board akd4104 demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. mclk 1 bick 2 sdti 3 lrck 4 pdn 5 csn 6 cclk 7 cdti 8 tx 16 cdto 15 vdd 14 vss 13 test4 12 test3 11 test2 10 test1 9 master clock ak4104 fs 24bit audio data reset & power down 64fs 0.1u + a nalog suppl y 2.7 to 3.6v 10u optic transmitting module micro controller figure 19. typical connection diagram (mode= ?0?, 4 wire mode ) mclk 1 bick 2 sdti 3 lrck 4 pdn 5 csn 6 cclk 7 cdti 8 tx 16 sdti2 15 vdd 14 vss 13 test4 12 test3 11 test2 10 test1 9 master clock ak4104 fs 24bit audio data1 reset & power down 64fs 0.1u + a nalog suppl y 2.7 to 3.6v 10u optic transmitting module micro controller 24bit audio data2 figure 20. typical connection diagram (mode= ?1?, 3 wire mode )
[ak4104] ms0642-e-01 2010/09 - 19 - package 0-10 detail a seating plane 0.10 0.17 0.05 0.22 0.1 0.65 *5.0 0.1 1.1 (max) a 1 8 9 16 16pin tssop (unit: mm) *4.4 0.1 6.4 0.2 0.5 0.2 0.1 0.1 note: dimension "*" does not include mold flash. 0.13 m package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ak4104] ms0642-e-01 2010/09 - 20 - marking akm 4104et xxyyy 1) pin #1 indication 2) date code : xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code : 4104et 4) asahi kasei logo revision history date (yy/mm/dd) revision reason page contents 07/07/09 00 first edition 10/09/28 01 specification change 19 package the package dimension was changed.
[ak4104] ms0642-e-01 2010/09 - 21 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporatio n of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distri butes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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